1. Field of the Invention
The present invention relates to a method of forming a silicon oxide layer in a semiconductor manufacturing process. More particularly, the present invention relates to a method of forming a silicon oxide layer having a good property by applying a polysilazane-based spin on glass (SOG) composition and applying an appropriate condition in forming an insulation layer.
2. Description of the Related Art
Recently, rapid advances have been made in the design of semiconductor devices as information media such as computers are widely spread. In particular, this progress has required semiconductor devices to function with a high operating speed, and to have a large storage capacity. In order to meet such requirements, semiconductor devices with increased density, reliability, and response time are under development.
For manufacturing an integrated circuit, a large number of active devices are formed on a single substrate. First, after each device is insulated, some devices are electrically interconnected during the semiconductor manufacturing process to accomplish a desirable function of the circuits. MOS and bipolar VLSI and ULSI devices have multilevel interconnection structures in which a large number of devices are interconnected.
In such a multilevel interconnection structure, the topography of a top layer generally becomes more uneven as the number of layers increases. For example, a semiconductor wafer having two or more metal layers may be formed in the following manner. A number of oxide layers, a polycrystalline silicon conductive layer and a first metal wiring layer are formed on a semiconductor wafer and then an insulation layer is formed on the conductive layer and the first metal layer. Then, a via hole is formed for the integration of a second metal layer. Here, the surface of the insulation layer is uneven because layers underlying the insulation layer are uneven. When the second metal layer is directly formed on the insulation layer, the second metal layer is liable to make fractures owing to protrusions or recesses of the insulation layer. Such a deposition state of the second metal layer generates a decreased yield of the semiconductor device. Therefore, before the formation of the via hole or the second metal layer that will be formed in the multilevel metal interconnection structure, a planarization process of the insulation layer is required.
To planarize the insulation layer, various methods have been developed. For example, a method utilizing a boro-phosphor silicate glass (BPSG) layer, which has a good reflow characteristic, a method utilizing an SOG layer, or a method utilizing a chemical mechanical polishing (CMP) process may be used.
In general, BPSG is widely used as a material for forming an insulation layer to fill a gap between metal wirings. However, there are problems associated with BPSG deposition. One such problem is in establishing the proper apparatus and chamber state. Another problem is that the gases used in BPSG deposition are expensive and severely toxic to humans.
Furthermore, as the degree of integration increases and the design rule gradually decreases for manufacturing VLSI having 256 MDRAM or more, using BPSG as the insulation layer to fill the gaps between wirings lowers the yield of the device due to the generation of voids and bridges. In addition, an etch stop layer subsequently formed may be damaged during subsequent processes. In order to solve these problems, a reflowing and an expensive CMP process should be additionally performed.
To avoid the problems associated with BPSG, materials having a good gap filling property, such as tetra ethyl ortho silicate (TEOS), undoped silicate glass (USG) and high density plasma enhanced chemical vapor deposition (HDP-CVD) oxide, may be used instead. However, layers formed by using these materials also are liable to generate voids or seams when applied to a device having a design rule of which critical dimension (CD) is about 0.18 μm or less.
On the contrary, a planar insulation layer may be formed through a simple coating process using SOG. When coating, because the SOG is in a liquid or SOL state, the SOG has a good gap filling property and a good effect of reducing a step.
Among SOG materials, a silazane-based material has a chemical formula of —(SiR1R2NR3)n— and has a mean molecular weight of from about 1,000 to about 10,000. Perhydropolysilazane is obtained when all of the parameters R1, R2 and R3 are hydrogen, and an organic polysilazane is obtained when the parameters R1, R2 and R3 are an alkyl, aryl or alkoxy functional group having 1–8 carbon atoms. One of these materials is included in an organic solvent such as dibutyl ether, toluene and xylene in a constant weight amount by % and then utilized for the coating process. The SOG coating material, called polysilazane in general, may be heat treated at a relatively higher temperature than silicate or siloxan-based materials. Accordingly, more complete curing is obtainable, and the coated material is highly resistant to wet etching, thereby facilitating subsequent processes. A polysilazane layer may be formed thick, and a planarization degree on the entire surface of a substrate can therefore be improved. As a result, it is not necessary to form a capping oxide layer on the polysilazane prior to a subsequent process such as a CMP process.
Various methods of preparing polysilazane are well known in the art. By one typical method, polysilazane is prepared by reacting halo-silane with a Lewis base to obtain a complex compound, and then reacting the complex compound with ammonia.
Also known is a method of preparing polysilazane by reacting a polyaminosilane compound with a polyhydrogenated nitrogen-containing compound under a base catalyst, or by reacting a polyhydrogenated silicon compound with a polyhydrogenated nitrogen-containing compound under a basic solid oxide catalyst.
Polysilazane may also be prepared by various other methods including reacting silicon halide such as SiCl4 or SiH2Cl2 with amine, transforming silazane into polysilazane utilizing an alkaline metal halide catalyst, dehydrogenating from a silane compound utilizing a transition metal complex compound and an amine compound, and the like.
A defoamed polysilazane may be prepared by utilizing inorganic polysilazane of which a number average molecular weight is from about 100 to about 100,000. Another method includes preparing perhydropolysilazane of which a number average molecular weight is 1,120.
Various methods for forming a silicon oxide layer using polysilazane include forming a polysilazane layer, and then firing the polysilazane layer under an oxygen atmosphere to be transformed into the silicon oxide layer. Another method includes depositing an inorganic SOG, and then performing two-step heat treatment processes to transform the SOG layer into the silicon oxide layer.
The basic bone of polysilazane-based SOG is composed of Si—N, Si—H and N—H bonds. The Si—N bonds are substituted with Si—O bonds by baking under an atmosphere including oxygen and water. A simple spin coating process and a simple curing process are performed for the transformation of the SOG layer into the silicon oxide layer. Accordingly, it is an economic method. In addition, this method is advantageous in overcoming a step generated by a gap between underlying patterns.
However, it is known that all of the Si—N bonds are not substituted with Si—O bonds. Accordingly, insulating and electrical characteristics of a silicon oxide layer prepared from an SOG layer are different from those of a silicon oxide layer such as a BPSG layer or a TEOS layer. As a result, using an SOG layer as an insulating layer is avoided.
In addition, because the SOG is deposited by a spin coating method, the thickness of a silicon oxide layer formed therefrom is insufficient to completely cover underlying conductive layers such as a gate electrode and a metal wiring.
Therefore, the inventors of the instant application have developed an SOG composition that can be completely transformed into silicon oxide. After coating polysilazane, a solvent component is removed through a baking process. Then, a curing is implemented through a heat treatment at a high temperature of about 600° C. However, silane gas (SiH4) starts to generate at about 400° C. from the coated layer and a large amount of the silane gas is exhausted during the heat treatment at the high temperature to combine with other exhausted components including nitrogen and a surrounding gas including oxygen. Accordingly, a large amount of particles having a size of about several hundreds of angstroms constituting a silicon nitride layer or a silicon oxide layer is formed on the surface portion of the substrate and on the inner portion of processing equipment. In addition, not only do the particles generate a particle defect on the corresponding substrate, but also on another substrate waiting to be processed in the same equipment.